1. Field of the Invention
The present invention relates to a method of critical dimension control, and particularly to a method of inter-field critical dimension control for a wafer in semiconductor technique.
2. Description of the Related Art
A critical dimension (CD) of a circuit is commonly defined as the smallest width of a line or the smallest space between two lines. Generally, the critical dimension is an important factor for the wafer manufacturing process. FIG. 1 shows a scheme of a wafer 100, which has a plurality of dies (or fields) 10. Generally, control of the critical dimension of the wafer 100 includes intra-field CD control and inter-field (or die-to-die) CD control. The intra-field CD control refers to control of the critical dimension in a individual die 10, so that the line width in the individual die 10 has approximately the same value. Meanwhile, the inter-field CD control refers to control of the critical dimension between the dies 10, so that the line width has approximately the same value among the dies 10.
When the inter-field critical dimension control applied to the wafer 100 is not preferred, the line width among the dies 10 of the wafer 100 varies. This reduces the stability of the semiconductor chips obtained by the dies 10. Consequently, the inter-field critical dimension control relates to the consistence of the die quality on the wafer.
Wafer manufacturing includes a plurality of individual processes, such as deposition, coating, exposure, developing, baking, and etching. An example of the wafer manufacturing process is described with reference to FIG. 2. In FIG. 2, the wafer 100 is sent into the film deposition chamber 20 for film deposition and moved to the bottom anti-resist coating (BARC) layer chamber 30 for bottom anti-resist coating. Then, the wafer 100 is moved sequentially to the resist coating chamber 40, the soft baking hot plate 50, the stepper 60, the hard baking hot plate 70 and the developing chamber 80 for resist coating, soft baking, exposure, hard baking, and developing. Finally, the wafer 100 is obtained by performing resist etching in the etching chamber 90 to finish the wafer manufacturing process.
In the above-mentioned process, any of the individual process can affect the inter-field critical dimension of the wafer. For example, uniformity of the resist coating layer determines the line width uniformity among the dies, and temperature difference during baking can affect the line width on the wafer at a rate of approximately 6 to 10 nm/° C.
In conventional critical dimension control, a plurality of experiments analyze each individual process in the above-mentioned wafer manufacturing process, so that a critical process has been obtained to perform calibration to improve the critical dimension control.
For example, U.S. Pat. No. 5,926,690 disclosed a run-to-run control process for the critical dimension control. The process employs a control system using photoresist etching time as a controlling variable in either a feedforward or a feedback control configuration to control critical dimension variation during semiconductor fabrication.
Another conventional example is disclosed in U.S. Pat. No. 6,063,530, where a method of critical dimension control through measurement of absorbed radiation is disclosed. In this prior art, a lithographic system with a detector for determining the amount of energy absorbed by the photoresist is applied. This enables the lithographic system to expose each field with the required exposure dose, thus reducing variations in the critical dimension.
Further, U.S. Pat. No. 6,529,623 disclosed a technique of stepper lens specific reticle compensation for the critical dimension control. In this prior art, the reticle is modified to produce an error which is selected to cancel the error that is being produced by the lens aberration so as to obviate the problem in which localized lens aberration causes a pattern of low yield which cannot be corrected by conventional stepper correction/adjustment and which leads to the determination that the stepper lens is the source of the problem. The modified reticle is then dedicated to the particular stepper.
Another conventional example is disclosed in U.S. Pat. No. 6,528,331, where a method for identifying and controlling impact of ambient conditions on the photolithography processes is disclosed. The method in this prior art includes the steps of: identifying a disturbance in a photolithographic process arising from an ambient condition; modeling the identified disturbance; and applying the model to modify a control input parameter. Since potential disturbances may be identified by characteristic data patterns or may be identified as known consequences to modifications to the critical dimension control, the model obtained in this method describes how the change in the critical dimension control affects the overlay performance.
However, in the above-mentioned prior arts, it should be mentioned that the apparatus used in the wafer manufacturing process generally includes a plurality of manufacturing devices for an individual process. In FIG. 2, for example, the film deposition chamber 20 includes three chambers DP1, DP2 and DP3; the BARC chamber 30 includes two chambers BARC1 and BARC2; the resist coating chamber 40 includes two chambers RC1 and RC2; the soft baking hot plate 50 includes three plates SHP1, SHP2 and SHP3; the stepper 60 for exposure includes three steppers STP1, STP2 and STP3; the hard baking hot plate 70 includes three plates HHP1, HHP2 and HHP3; the developing chamber 80 has two chambers DVP1 and DVP2; and etching is performed in two etching chambers, ETCH1 and ETCH2.
It is obvious that a difference exists among manufacturing devices for each of the individual process and the difference may affect the critical dimension control in the wafer manufacturing process. Further, it is difficult to find a critical process for wafer manufacture since each of the individual process may use different manufacturing devices. In FIG. 2, by combination of the manufacturing devices for the whole wafer manufacturing process, a group of 1296 manufacturing modules is obtained. Consequently, it is not possible to improve the inter-field critical dimension by calibration of any individual process.